About
As the system complexity of electronic digital systems grows, a new systematic design methodology, called codesign, has been sought for targetting diverse architectures from system-on-chip to distributed heterogeneous systems. The main feature of codesign environment is to co-specify, co-simulate, and co-synthesize modules with different characteristics in the same framework. The PeaCE project aims to cover the multi-facets of codesign tasks: codesign of hardware and software modules, and codesign of control and function modules. Even though it is developed as a University research project, it targets for applying a new design methodology in the real system design. To use PeaCE for a real system design, you have to customize the environment somewhat though we are making best efforts to minimize such customizing work for fast system development.
The key features are as follows.
1. Open-source framework to promote collaboration of system level design researches. For example, a new partitioning algorithm can be easily incorporated into the design procedure and compare with other approaches. We hope many research groups exchange their ideas and research results on the same experimental environment.
2. Reconfigurable framework to integrate third party design tools into the environment. For this purpose, we try to decouple the design steps as much as possible, using file interface between design steps. For example, a new partitioning algorithm can be easily incorporated into the design procedure and compare with other approaches. And we have tested seamless interface with Seamless CVE cosimulation tool.
3. Separate Java based GUI (Hae) from kernel. The user interface is platform independent, and user friendly with MS Windows' style. Web-based user interface will be provided.
4. Objected-oriented C++ kernel inherited from the Ptolemy project. Decoupled from the user interface, the kernel is designed for high performance with more maintenance requirements.
5. Multilingual system design. How to specify the system in the design framework has been a long debate issue. Our position is to use multiple languages and define carefully how to integrate them for a single system design. PeaCE uses different models of computations for functional and control representations: dataflow (SPDF) graphs for function representation and FSM (fFSM)for control representation. They reside in yet another model of computation for the codesign backplane.
6. Automatic hardware/software synthesis. We will show how to generate VHDL codes and C codes from the initial specification models: concurrent FSM (fFSM) and Synchronous Piggybacked Dataflow (SPDF). The synthesized code will be downloaded and executed on the prototyping boards.
